1. Field of the Invention
The present invention relates to a digital to analog converter, to a return-to-zero digital to analog converter with improved wideband characteristics by enabling a return-to-zero output without separate clock and controller, and a converting method thereof.
2. Description of the Related Art
With the advent of high speed wideband processing system with development of information communications, there is an increasing need of a digital to analog converter (DAC) which is capable of synthesizing analog signals of a desired frequency band at high speed and accordingly the number of applications to which such a DAC is applied is increasing.
FIG. 1 shows a configuration of a general high speed DAC 10. As shown, the high speed DAC 10 includes a thermometer decoder 13 for promptly selecting a switch corresponding to input digital information in order to increase a selection speed of a current switch 17 connected to a current source 16, and pipelines 12 and 15 using flip-flops for process of individual words.
In more detail, input p-bit digital data are first provided to the first pipeline 12 through an input buffer 11. Then, some upper q bits in the p-bit digital data are delivered to the second pipeline 15 through the thermometer decoder 13 which outputs the upper q bits as bits of the combinable number of (2q−1), while the remaining (p−q) bits are delivered to the second pipeline 15 through a delay block 14 which delays a process time of the thermometer decoder 13 for the purpose of processing the (p−q) bits along with the q bits. An output ((2q−1)+(p−q) bits) of the second pipeline 15 which processes outputs of the thermometer decoder 13 and the delay block 14 in parallel is used as a control signal of the current switch 17 to selectively output the current source 16 connected to the current switch 17, thereby providing a desired output current with a combination of segment current.
The current switch 17 and the current source 16 may be configured using various schemes, including, for example, a scheme of connecting switches to respective non-linear current sources to provide a desired output current, a scheme of outputting unit current sources through a combination of switches to provide a desired output current with a combination of outputs thereof, a scheme of operating switches to which linear current sources having respective weights based on binary values are connected to provide a desired output current with a combination of outputs thereof, a scheme of combining two or more of the above-mentioned schemes to provide a desired output current, etc.
The DAC 10 is operated in synchronization with clocks which provide operation periods of the first and second pipelines 12 and 15, and accordingly such a clock speed becomes an operation speed of the DAC 10. If an output of the DAC 10 is an NRZ (Non-Return-to-Zero) output, a discontinuous reference between output currents provided per clock becomes a clock period, which may limit a degree of precision. In order to overcome such a Nyquist band limitation (that is, a limitation of a use band to a clock frequency) and cope with a high speed wideband, up-converters must be connected in series, which may result in complexity of configuration.
As another method for achieving a high speed and wideband DAC, a configuration of converting an NRZ output to a RZ (Return-to-Zero) output may be additionally employed to extend a Nyquist band.
FIG. 2 shows examples of an NRZ output and a RZ output. As shown, placing an NRZ output signal in the left side of the figure on a zero point (0) one time per unit period as shown as an RZ output signal in the right side of the figure can double a Nyquist band. Accordingly, it is possible to achieve a wideband output without an additional up-converter.
FIG. 3 shows a partial configuration of an existing DAC for RZ output, where a switch 20 which provides a current source as an output is controlled by an RZ control signal.
Specifically, the existing DAC is configured such that a separate RZ controller 21 is added to control the switch 20 to output a ground potential every a period of clock for a predetermined time, while a control signal produced for DAC output (that is, switch selection data obtained from input digital data) is provided to the switch 20. The RZ controller 21 receives an RZ control signal and controls an output of the switch 20 to be an zero point (0) every a period of input clock based on the received RZ control signal. In this case, it is commonly configured such that the RZ output is automatically provided through the switch 20 according to a signal provided by the RZ controller 21 and a clock signal, and most of the RZ output provided through the switch 20 is forced to be the zero point during half or so a clock period.
However, such a configuration has to employ the above-mentioned separate RZ controller 21 and provide a signal which provides the RZ controller 21, which may result in increase in its load to be controlled, increase in power consumption for operation of the controller 21, and complexity of the configuration. In addition, since the clock signal, which is a digital signal, is directly coupled to the switch 20 for generating an analog signal, noise of the clock signal has an effect on the analog signal, which results in deterioration of system stability. In particular, if an output signal is forced to be coupled to a ground in order to put the output signal on a zero point using the clock signal, dynamic performance is deteriorated due to noise of the clock signal.
As an alternative, as shown in FIG. 4, it may be configured that, in addition to providing a control signal (that is, switch selection data obtained from input digital data) generated for DAC output to the switch 30 configured to provide RZ output, a re-sampling clock faster than the system clock is further provided to the switch 30, so that a current of the current source coupled to an output of the switch 30 can alternate with a zero point by the re-sampling clock.
However, since such a configuration also requires a configuration for generating the additional re-sampling clock for the RZ output and the re-sampling clock is directly provided to the RZ switch 30 which is an analog circuit, noise of the re-sampling clock has an effect on the analog signal, which results in deterioration of system stability.
In this manner, the existing configurations for RZ output require separate controller configurations or clocks, and when the existing configurations use the scheme of coupling an output signal to a ground using clocks, there arise a problem of deterioration of dynamic performance due to clock noise. Accordingly, there is an increasing need for an RZ DAC with efficient power consumption and size and improved dynamic performance.